The present invention relates to a high pin count and multi-layer wiring lead frame for resin sealed semiconductor devices, and particularly to a high pin count and multi-layer wiring lead frame which achieves high density of the conductive bond locations of an IC device, and has excellent transmission characteristics and outer leads with predetermined rigidity.
In the prior art, a lead frame for semiconductor devices consists of a single-layer lead frame made of metal formed on a flat plate to reduce the size of semiconductor packages. This single-layer lead frame has a simple shape. However, since terminals for power supply to lead frames and semiconductor elements and terminals for signals are placed close to each other on the same plane, electromagnetic interferences between the terminals occur. That is, a crosstalk occurs when high frequency signals are transmitted, thus making it impossible to achieve good transmission characteristics. In addition, as the lead frame is not provided with a grounding layer which can remove an induction current properly, capacitance becomes large with the result of deteriorated transmission characteristics.
A multi-layer lead frame wherein an insulating layer is sandwiched between a grounding layer and a power supply layer, and the grounding terminal and power supply terminal of a semiconductor element are bonded to the grounding layer and power supply layer, respectively, to overcome this problem, has recently been reported.
However, this multi-layer lead frame is also a metal frame having inner leads integrated with outer leads. Therefore, the thickness of this type of lead frame should not fall below a certain level in order to achieve strength, with the result that the whole lead frame becomes bulky.
In addition, as the high-density arrangement of inner leads at the tip thereof is difficult for punching, the pitch of the inner leads of the lead frame should be beyond a certain level. For instance, a lead frame with a thickness of 0.10 mm has a limit pitch of 0.18 mm. That is, it has been impossible to further increase the inner lead counts.
Tape Pac QFP (Quad Flat Package) manufactured by NSC of the US is an example of a lead frame which has a greater number of leads due to shortened wire lengths. This package has a TAB tape carrier structure wherein LSI elements and leads are connected by the gang bonding method. However, since the package has only a single wiring layer, transmission speed cannot be increased.
When a lead frame has a large number of lead terminals, the transmission characteristics of the lead frame becomes more important.
In such a lead frame, various devices are provided to improve transmission characteristics in the case that high frequency signals are applied, in addition to the fine line definition of high density lead fingers.
Generally, the delay time (T.sub.0) of the high frequency signal is represented by the following equation: EQU T.sub.0 =.iota..multidot.C.sub.0 .multidot.Z.sub.0 =.iota..multidot.L.sub.0 .multidot.C.sub.0
where .iota. represents wire length, C.sub.0 capacitance, Z.sub.0 impedance and L.sub.0 inductance. ##EQU1## where .epsilon..sub.r is permittivity, w wire distance and d the thickness of an insulating layer.
As understood from the above equations, when the high-frequency signal is applied, the delay time is mainly relative to capacitance and impedance.
However, the capacitance and inductance of the single-layer metal lead frame of the prior art relative to the delay time cannot be reduced sufficiently.